The lectures will be held on Tuesday, 23rd May 2023 at 2 p.m.

Saburo Muroga Professor Josep Torrelas from the University of Illinois, Urbana-Champaign, USA will hold the lecture titled “Cloud Computer Architecture for the Next Decade” and Professor Veljko Milutinović from the University of Indiana, Bloomington, USA will hold the lecture titled “DataFlow SuperComputing for Big Data Deep Analytics”.

The abstracts of lectures and biographies of lecturers you can read below:

Lecture starting at 2 p.m.

DataFlow SuperComputing for Big Data Deep Analytics

Abstract

This presentation analyses the essence of DataFlow SuperComputing, defines its advantages and sheds light on the related programming model that corresponds to the recent Intel patent about the future Intel’s dataflow processor. The stress is on issues of interest for General Engineering and on the problems of interest for this audience. Acording to Alibaba and Google, as well as the open literature, the DataFlow paradigm, compared to the ControlFlow paradigm, offers: (a) Speedups of at least 10x to 100x and sometimes much more (depends on the algorithmic characteristics of the most essential loops and the spatial/temporal characteristics of the Big Data Streem, etc.), (b) Potentials for a better precision (depends on the characteristics of the optimizing compiler and the operating system, etc.), (c) Power reduction of at least 10x (depends on the clock speed and the internal architecture, etc.), and (d) Size reduction of well over 10x (depends on the chip implementation and the packiging technology, etc.). The bigger the data, and the higher the reusability of individual data items (which is typical of ML), the higher the benefits of the dataflow paradigm over the control flow paradigm. However, the programming paradigm is different, and has to be mastered.

Speaker

Professor Veljko Milutinovic received his PhD from the University of Belgrade in Serbia, spent about a decade on various faculty positions in the USA (mostly at Purdue University and more recenlty at the Indiana University in Bloomington), and was a co-designer of the DARPAs first GaAs (Gallium Arsendie) RISC microprocessor at 200MHz (about a decade before commercial efforts on the same speed) and the DARPAs first GaAs Systolic Array with 4096 processors on 200MHz (both well documented in the open literature). Later, for about three decades, he taught and conducted research at the University of Belgrade, in EE, MATH, MBA, and SCI. Now he serves as the Chairman of the Board of IPSI Belgrade (a spin-off of Fraunhofer IPSI from Darmstadt, Germany). His research is mostly in datamining algorithms and dataflow computing, with the emphasis on mapping of big data algorithms onto fast emerging technologies and energy efficient architectures. For 20 of his edited books and related publications, focused forewords or condensed wisdom were contributed by 20 different Nobel Laureates with whom he cooperated on his past industry sponsored projects.

Lecture starting at 3 p.m.

Cloud Computer Architecture for the Next Decade

Abstract

The Cloud of the next decade will be defined by the need to process vast swaths of data for insights in a timely manner. Minimizing data movement to curtail energy consumption and increasing computation efficiency will be the overriding constraints. The compute infrastructure will be a seamless hierarchy of compute centers from edge to geo-distributed mega-datacenters. Each compute center will contain a large number of heterogeneous hardware accelerators, and tasks of unprecedentedly small granularity will ship computation to where data is. In this talk, I will describe some of the research on computer systems that my group is performing to attain this vision. We are developing programmable accelerators organized into ensembles, heterogenous memory systems, smart network interfaces and secure hardware structures. The combination of all these technique is likely to deliver large improvements in performance and energy efficiency.

Speaker

Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois Urbana-Champaign (UIUC). He is the Director of the SRC/DARPA ACE Center for Evolvable Computing, past Co-Leader of an Intel Strategic Research Alliance (ISRA) on Computer Security, and past Director of the Illinois-Intel Parallelism Center (I2PC). His research interests are computer architectures for shared-memory multiprocessors and parallel computing. Some of his contributions include thread-level speculation (TLS) architectures, the Bulk Multiprocessor concept, deterministic record and replay mechanisms, process variation mitigation techniques, and hardware defenses against speculative execution attacks. In addition, he has contributed to several experimental multiprocessor designs such as IBM’s PERCS Multiprocessor, Intel’s Runnemede Extreme-Scale Multiprocessor, Illinois Cedar, and Stanford DASH. He has graduated 48 PhDs, who are now leaders in academia or industry.